Wafer reconfiguration

ABSTRACT

At least one water is embedded in a carrier to eliminate or at least reduce edge effect. The wafer reconfiguration is designed to improve a quality not only for spin coating process but also for electric plating process. An edge bead is formed on top of the carrier instead of being formed on top of the wafer so that a full top surface of the wafer can be active to the fabrication of chips and therefore more chips are yielded for a single wafer. The backside of the wafer is not contaminated by the coating according to the present invention. Further, dummy circuits can be made on top of the carrier so that electric plating uniformity tor full area of a wafer can be improved.

BACKGROUND

1. Technical Field

The present invention relates to wafer reconfiguration, especially for awater embedded in a carrier to eliminate or at least reduce edge effectto provide improvement not only for spin coating process but also forelectric plating process.

2. Description of Related Art

FIGS. 1, 2A˜2B Show a Prior Art

FIG. 1 shows that U.S. Pat. No. 8,192,555 discloses a spin coatingprocess for spreading photoresist onto silicon wafers, FIG. 1 shows thata photoresist dispenser 12 is configured on top; photoresist 108 isdispensed on a top surface of a wafer 10. The wafer 10 is mounted on avacuum chuck 101. A spindle 102 is configured on bottom of the vacuumchuck 101 to spin the wafer 10 during spin coating process.

FIG. 2A shows that the spin coating procedure makes an edge bead 107 beformed on top at the peripheral of the wafer 10. Further, thephotoresist 108 quite often wraps around the wafer 108 contaminating thebackside 1072 of the wafer 108 as well.

FIG. 2B shows that the edge bead 107 is then removed in a later process.A circular peripheral area 105 of the wafer 10 is exposed. The Edge BeadRemoval (EBR) process leaves uniform thickness of photoresist coatingacross the wafer 10 except for the circular peripheral area 105. Theuniform photoresist coating allows for proper focus of light onto thecoated wafer during a photolithography process to design themicroelectronic circuits. However, the edge bead removal (EBR) reducesthe active area of a wafer and hence reduces chip yields, FIG. 2B showsthat an active area 106 smaller than a full top surface of the wafer 10can be used for the fabrication of chips. FIG. 2B shows the backsidephotoresist contamination of the wafer 10 has been removed also. Thebackside photoresist removal takes additional time and cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1, 2A˜2B show a prior art

FIGS. 3A˜3B show a first embodiment according to the present invention.

FIGS. 4A˜4B, 5A˜5B, 6A˜6B, 7˜10 show a process for preparing a waferreconfiguration of FIG. 3A.

FIG. 11 shows a second embodiment according to the present invention.

FIG. 12 shows a third embodiment according to the present invention.

FIGS. 13A˜13B show wafer reconfiguration for a single wafer according tothe present Invention.

DETAILED DESCRIPTION OF THE INVENTION

A wafer reconfiguration is disclosed to improve quality not only forspin coating process hut also for electric plating process. The waferreconfiguration shows that at least one wafer is embedded in a carrier.Such a wafer reconfiguration facilitates edge bead, be formed on Cop ofthe carrier instead of being formed on top of the wafer during spin,coating process. Further, dummy circuits can be made on top of thecarrier to improve uniformity of plating thickness during platingprocess.

According to the present invention, a carrier is prepared with, at leastone through space for a wafer to be embedded in. Sealing material fillsinto the gap between the wafer and the carrier. The sealing materialbridges the top surface of the carrier and the top surface of the waferso that the photoresist may spreading over the top of the wafer andextends to the top surface of the carrier to leave a circular edge beadon top of the carrier.

Since the edge bead locates on top of the carrier, a later removal ofthe edge bead shall reduce damage to the wafer and still keep a full topsurface of the wafer to be active so that full area of the wafer can beused to the fabrication of chips and hence to increase the chip yield.

FIGS. 3A˜3B Show a First Embodiment According to the Present Invention

FIG. 3A shows a wafer reconfiguration for two wafers embedded in acarrier in a section view.

FIG. 3A shows that a carrier 25 has two through spaces; each spaceaccommodates one of the wafer 201, 202. A thickness of the carrier 25equals to or closes to the thickness of the wafer 201, 202. Sealingmaterial 222 fills in a gap 22 between each wafer 201, 202 and thecarrier 25. The sealing material 222 bridges a top surface of thecarrier 25 and a top surface of the wafer 201, 202. A photoresist 108 iscoated on top of the wafer 201, 202 and on top of the carrier 25 throughspin, coating process. FIG. 3A shows that a uniform thickness of thephotoresist 108 covers a top of both wafers 201, 202. The photoresist108 also covers most top of the carrier 25. An edge bead 207 is formedon top of the carrier 25 in a circular peripheral area. Please payattention that the edge bead 207 is formed on an area outside a top ofboth wafers 201, 202 from a top view. In other words, the circular edgebead 207 is formed surrounding both wafers 201, 202 from a top view.Since uniform thickness photoresist 108 formed on top of the full topsurface of both wafers 201, 202 so that the full top surface of bothwafers 201, 202 can be used to the fabrication of chips. The full topsurface of each wafer 201,202 is a full active area 206 which can beused for the fabrication of chips. The active area 206 for the presentinvention is larger than, the active area 106 of the prior art FIG. 2B,therefore the present invention yield more chips than the conventionalone while under same process conditions.

Further, the photoresist wraps around the carrier 25, if anycontaminating the backside 2072 of the carrier 25 only, instead ofcontaminating the backside of the wafer 201, 202.

FIG. 3B shows that the circular edge bead 2.07 is removed in a laterstep while leaving a central area with a uniform thickness of thephotoresist 108 on top of both wafers 201, 202. The EBR process leaves acircular area 205 on top of the carrier 25 without having photoresist108. The circular area 205 surrounds the wafers 201, 202. Each of thewafers 201, 202 has an active area 206 according to the presentinvention. In other words, the full surface of the wafer 201, 202 can beused to the fabrication of chips.

FIGS. 4A˜4B, 5A˜5B, 6A˜6B, 7˜10 Show a Process for Preparing a WaferReconfiguration of FIG. 3A

FIG. 4A shows a carrier 25 having four through spaces 251, 252, 253, 254formed therein; each space is designed to accommodate a water forprocess. A tape 26 is configured on bottom of the carrier 25 for sealingthe through spaces 251, 252, 253, 254 from bottom,

FIG. 4B shows a section view of FIG. 4A according to line AA′. FIG. 4Bshows that a tape 26 is configured on bottom of the carrier 25.

FIG. 5A shows that four wafers 201˜204, each is configured in one of thespaces 251˜254. A gap 22 is formed between each wafer 201˜204 and thecarrier 25,

FIG. 5B shows a section view of FIG. 5A according to line 8B FIG. 5Bshows that a gap 22 is formed between each wafer 201˜204 and the carrier25.

FIG. 6A shows a sealing material 222 filling in the gap 22 to bridge thetop surface of the wafer 201˜204 and the top surface of the carrier 25.

FIG. 7 shows that the tape 26 is removed from the product of FIG. 6B andthen configured on top of the vacuum chuck for spin coating process.

FIG. 7 shows that the carrier 25, wafers 201˜204, and the sealingmaterial 222 are made coplanar.

FIG. 8 shows that photoresist dispenser 12 is configured on top, and thephotoresist 108 is then coated on top of the wafer 201˜204 during spin.

FIG. 9 shows that a circular edge bead 207, however only two edge beadsare shown in the section view, is formed on top of the carrier 25 in theperipheral area. The circular edge bead 207 encircles an area on toplarger than an area occupied by the four wafers 201˜204 from a top view.In other words, the circular edge bead 207 locates at an area outside anarea where the four wafers 201˜204 occupied from a top view, so that auniform thickness photoresist 108 covers a full top surface of thewafers 201˜204. Further, the photoresist wraps around the carrier 25, ifany, contaminating the backside 2072 of the carrier 25 only, instead ofcontaminating the backside of the wafer 201˜204.

FIG. 10 shows a top view of FIG. 9.

FIG. 10 shows that the photoresist 108 is coated on top of the carrier25 to cover top of the four wafers 201˜204, A circular edge bead 207configured at a peripheral of the photoresist 108. The circular edgebead 207 is configured on a top of the carrier 25. The circular edgebead 207 does not cover top of the wafers 201˜204 from a top view. Theflat and uniform thickness photoresist 108 covers an area larger than,the full top surface of the wafers 201˜204.

FIG. 11 Shows a Second Embodiment According to the Present Invention

The wafer reconfiguration according to the present, invention alsoimproves plating uniformity. FIG. 11 shows that the carrier 25 can beone of Copper Clad Laminate (CCL) or Alloy 42. The surface metal of thecarrier functions as dummy circuitry 28 so that electric field can beevenly distributed to enhance the plating uniformity of the circuitry inthe wafer during plating.

FIG. 12 shows a Third Embodiment According to the Present Invention

FIG. 12 shows carrier 252 is made of glass, then a dummy circuit 28 areformed on top of the glass carrier 252 so that electric field can beevenly distributed to enhance the plating uniformity of the circuitry inthe wafer during plating.

FIGS. 13A˜13B Show Wafer Reconfiguration for a Single Wafer According tothe Present Invention

FIG. 13A shows that a photoresist 108 is coated on top of the carrier 25and a circular edge bead 207 formed at a peripheral area of thephotoresist 108.

FIG. 13B shows a section view of FIG. 12A. A wafer 201 is embedded in acenter of a carrier 25, A sealing material 222 fills the gap 22 betweenthe wafer 201 and the carrier 25. A uniform photoresist 108 covers alarger area than the full, top surface of the wafer 201. After EBRprocess, full top surface of the wafer 201 can be active for thefabrication of chips.

Further, the photoresist wraps around the carrier 25, if any,contaminating the backside 2072 of the carrier 25 only, instead ofcontaminating the backside of the wafer 201.

According to the present invention, the wafer substrate can be made ofsilicon, glass, or aluminum. For which the Coefficient Thermal Expansion(CTE) is compatible with the CTE of the wafer substrate.According to the present invention, the carrier 25 can be Copper CladLaminate (CCL) or alloy 42(Nilo 42). Alloy 42 (Nile 42) is a nickel-ironcontrolled-expansion alloy containing 42% nickel. Alloy 42 (Nilo 42) hasa low and normally constant coefficient of thermal expansion from roomtemperature to about 300° C. (570° F.). According to the presentinvention, the sealing material, can be epoxy or silicone.

While several embodiments have been described, by way of example, itwill be apparent to those skilled, in the art that various modificationsmay be configured without departs from the spirit of the presentinvention. Such modifications are all within the scope of the presentinvention, as defined by the appended claims.

1. A wafer reconfiguration, comprising: a carrier; at least one waferreceived in a space in the carrier; and a sealing material filled in agap between the wafer and the carrier, wherein a top surface of thesealing material is coplanar with a top surface of the carrier and a topsurface of the wafer.
 2. A wafer reconfiguration as claimed in claim 1,further comprising: a uniform thickness coating covering an entirety ofthe top surface of the wafer.
 3. A wafer reconfiguration as claimed inclaim 2, further comprising: a circular edge bead configured in aposition outside the top surface of the wafer from a top view.
 4. Awafer reconfiguration as claimed in claim 1, further comprising: surfacemetal or dummy circuitry configured on the top surface of the carrier.5. A wafer reconfiguration as claimed in claim 1, wherein a bottomsurface of the carrier and a bottom surface of the wafer are coplanarwith a bottom surface of the sealing material.
 6. A waferreconfiguration as claimed in claim 1, wherein the carrier is made of amaterial selected from the group consisting of Copper Clad Laminate andalloy
 42. 7. A wafer reconfiguration as claimed in claim 1, wherein thesealing material is selected from the group consisting of epoxy andsilicone.
 8. A wafer reconfiguration as claimed in claim 1, wherein thewafer is made of a material selected from the group consisting ofsilicon, glass, and aluminum.
 9. A wafer reconfiguration as claimed inclaim 1, wherein the space extends through an entire thickness of thecarrier from the top surface of the carrier to a bottom surface of thecarrier, and a bottom surface of the wafer is exposed at the bottomsurface of the carrier.
 10. A wafer reconfiguration as claimed in claim1, wherein an entirety of the bottom surface of the wafer is exposed atthe bottom surface of the carrier.
 11. A wafer reconfiguration asclaimed in claim 1, wherein the sealing material extends around an outerperiphery of the wafer, and the carrier extends around an outerperiphery of the sealing material.
 12. A wafer reconfiguration asclaimed in claim 1, wherein the wafer is received in the space withoutbeing supported from below by any part of the carrier.
 13. A waferreconfiguration, comprising: a carrier; at least one wafer received in aspace in the carrier; and a sealing material filled in a gap between thewafer and the carrier, wherein each of the carrier, the wafer and thesealing material has, in a thickness direction of the carrier, a topmostsurface and a bottommost surface, the topmost surface of the carrier,the topmost surface of the wafer, and the topmost surface of the sealingmaterial are all coplanar with each other, the space extends through anentire thickness of the carrier from the topmost surface of the carrierto the bottommost surface of the carrier, and the bottommost surface ofthe wafer is exposed at the bottommost surface of the carrier.
 14. Awafer reconfiguration as claimed in claim 13, wherein an entirety of thebottommost surface of the wafer is exposed at the bottommost surface ofthe carrier.
 15. A wafer reconfiguration as claimed in claim 13, whereinthe bottommost surface of the carrier, the bottommost surface of thewafer and the bottommost surface of the sealing material are allcoplanar with each other.
 16. (canceled)
 17. A wafer reconfiguration asclaimed in claim 15, wherein the wafer is received in the space withoutbeing supported from below by any part of the carrier.
 18. A waferreconfiguration, comprising: a carrier; at least one wafer received in aspace in the carrier; and a sealing material filled in a gap between thewafer and the carrier, wherein each of the carrier, the wafer and thesealing material has, in a thickness direction of the carrier, a topmostsurface and a bottommost surface, the topmost surface of the carrier,the topmost surface of the wafer, and the topmost surface of the sealingmaterial are all coplanar with each other, the sealing material extendsaround an outer periphery of the wafer, the carrier extends around anouter periphery of the sealing material, and the wafer is received inthe space without being supported from below by any part of the carrier.19. A wafer reconfiguration as claimed in claim 18, wherein thebottommost surface of the carrier, the bottommost surface of the waferand the bottommost surface of the sealing material are all coplanar witheach other.
 20. A wafer reconfiguration as claimed in claim 19, whereinthe carrier is made of a material selected from the group consisting ofCopper Clad Laminate and alloy 42, the sealing material is selected fromthe group consisting of epoxy and silicone, and the wafer is made of amaterial selected from the group consisting of silicon, glass, andaluminum.